As electronic components are becoming smaller and smaller along with the internal structures in integrated circuits, it is becoming easier to either completely destroy or otherwise impair electronic components. In particular, many integrated circuits are highly susceptible to damage from the discharge of static electricity. Generally, electrostatic discharge (ESD) is the transfer of an electrostatic charge between bodies at different electrostatic potentials or voltages, caused by direct contact or induced by an electrostatic field. The discharge of static electricity, or ESD, has become a critical problem for the electronics industry.
Device failures resulting from ESD events are not always immediately catastrophic or apparent. Often, the device is only slightly weakened but is less able to withstand normal operating stresses. Such a weakened device may result in reliability problems such as increased leakage currents resulting in degraded performance of the device.
System-on-Chip (SoC) ICs are produced in advanced CMOS technologies where no gate oxides of appropriate thickness are available for cost reasons. In such applications, one challenge is to provide an ESD robust high voltage (HV) transistor element which has excellent mixed signal performance and gate oxide reliability.
Such HV devices should operate over a wide range of interface voltage, e.g., 5V to 12 V. Such wide interoperability allows them to used for applications such as for an input/output (TO) circuit implemented in a SoC.
One option is to use drain extended field effect transistors also referred as drain extended MOS devices (DeMOS) for IO drivers in SoC ICs. DeMOS transistors are asymmetric in the drain and source construction allowing large voltages to be directly applied to the transistor pads.
However, DeMOS transistors are ESD-weak and require additional protective circuitry to prevent damage from ESD. Additional ESD circuitry, however, increases the cost of the chip.
Therefore, to improve efficiency of silicon real estate and reduce the chip cost, DeMOS transistors with good ESD immunity are required.
FIG. 1 illustrates a conventional drain extended metal oxide semiconductor (DeMOS) (n-channel) transistor.
Referring to FIG. 1, a substrate 100 comprises a p-body region 10. A p-well region 20 and an n-well region 30 are disposed adjacent and have a common p-n junction as illustrated. Isolation regions comprising a drain sided isolation region 40 and other isolation regions 41 (e.g., STI—Shallow Trench Isolation) are formed within the substrate 100. The channel region 35 of the DeMOS transistor 1 is formed within the p-well region 20. A source region 50 having a n+ doping is disposed within the p-well region 20 of the substrate 100. A drain region 60 having a n+ doping is disposed within the n-well region 30 of the substrate 100. A substrate contact region 70 having a p+ doping is disposed within the p-well region 20 to contact the p-well region 20. A gate 80 is disposed between the source region 50 and the drain region 60. Spacers 45 are disposed on the sidewalls of the gate 80. Under normal operation as a field effect transistor (FET), e.g., when an inversion layer is formed within the channel region 35, the charge carriers from the source region 50 move across the channel region 35 and flow through an extended drain region 51 (shown by the arrow) around the STI corners before reaching the drain region 60. Thus portions of the n-well region 30 under the drain-sided isolation region 40 and the gate 80 form part of the drain of the DeMOS transistor 1.
As a consequence, the potential from the drain contact of the drain region 60 is dropped due to the increased resistance of the lower doped n-well region 30 that forms the extended drain region 51. The drain-sided isolation region 40 underneath gate-to-drain overlap is used to protect device from any gate oxide failure while applying high bias at the drain region 51. However, such a device configuration results into space charge modulation due to localized current distribution and cause a very early thermal failure of the device, which is attributed to filament formation. As will be described in detail below, this construction results in poor ESD performance requiring additional circuitry to protect the device against ESD damage.
Hence what are needed are devices that are robust against ESD stress.